Microprocessor with apparatus for parallel execution of instructions

摘要

A computer system includes a dual instruction decoder which issues two instructions in parallel within a single clock cycle if their are no register dependencies between the instructions, and instructions fall within a predetermined subset of the complete instruction set. The system includes first and second instruction pipelines. The first pipeline executes any instruction issued from the full instruction set, while the second pipeline only executes a predetermined subset of instructions selected based on principles of locality. A register dependency checker determines whether the destination register of a first instruction is used during the execution of a second instruction in an instruction sequence. When both instructions are within the subset and there are no dependencies, the first and second instructions can be issued in parallel in the first and second pipelines.