发明名称 |
Circuit arrangement with at least one input and at least one output for forwarding an input signal that can be filtered, parallelized and digitized |
摘要 |
A circuit arrangement (1000, 2000), preferably for a coupling network component of a network node in a packet-switching data network, is disclosed which has a wide parallelization of the data packet signal by means of shift registers (60), so that it is possible to operate internally with a greatly reduced operating speed. In particular, an arrangement of the components on a single semiconductor wafer (3000, 4000) permits an especially wide bus (20), which can be constructed extremely advantageously with a surface-optimized floor plan (3000, 4000).
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申请公布号 |
US5475708(A) |
申请公布日期 |
1995.12.12 |
申请号 |
US19940227901 |
申请日期 |
1994.04.15 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
LAWITZKY, GISBERT;MOELLER, WOLF-DIETRICH;SCHMITT, FRANZ-JOSEF |
分类号 |
H04L12/56;(IPC1-7):H04J3/24;H04J3/02 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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