| 摘要 |
<p>PURPOSE:To increase reliability for the check of a RAM in ATM communication equipment whose access frequency is disabled to estimate by checking again the RAM in which an error is detected by using the timing of an idle cell. CONSTITUTION:An address latch part 6, when detecting the error by a RAM check part, informs a RAM address in which the error is detected to an address storage part 7. The storage part 7 stores the RAM address in which the error is detected. An idle cell detecting part 8 always detects the idle cell, and informs it to a control part 4 when detecting the idle cell. The control part 4 performs the re-check of output of the RAM address stored in the storage part 7 by using the timing of a detected dead cell, and deletes it from the storage part 7 when it is a normal one. When no stored address exists, the check of the address is continued by address patrol, and when the number of stored and held addresses exceeds a prescribed value, the RAM is judged as a defective one.</p> |
