发明名称 TREE ADDER AND MULTIPLIER
摘要 PURPOSE:To provide a tree adder which is highly integrated and easily realizes the generation of an optional number of bits. CONSTITUTION:A cell 1 including a partial product generator and wires for shifting, a cell 2 including a partial product generator, a full-adder, and wires for shifting, a cell 3 including a unit adder and wires for fields, and a cell 4 including a half-adder are provided, and those cells 1-4 are arranged according to a specific arrangement algorithm to constitute tree adders 21 and 22. And, the full adder is included in the same cell with the partial product generator to increase the degree of integration of the tree adders 21 and 22, and since the tree adders 21 and 22 are constituted by using the specific arrangement algorithm, the tree adders consisting of the optional number of bits can easily be provided.
申请公布号 JPH07319670(A) 申请公布日期 1995.12.08
申请号 JP19940115345 申请日期 1994.05.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAI YUJI;MORIWAKI TOSHIYUKI
分类号 G06F7/509;G06F7/50;G06F7/506;G06F7/52;G06F7/53;G06F7/533 主分类号 G06F7/509
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