Clock signal generating circuit suitable for integrated circuit testing systems

摘要

A delay unit (120) comprises several variable delay elements (52) connected in series and each having a time delay smaller than a period of the clock signal. A phase comparator (140) compares the total delay from the least stage with the clock signal and giving a voltage to show the difference. A feedback unit (150) forms a PLL to ensure that the total delay equals a period of the clock signal.