Method for erasing an EEPROM flash memory cell and corresponding erasing circuit.

摘要

A method for erasing a plurality of non-volatile memory cells of the flash EEPROM type each comprising a floating gate transistor and incorporated in a memory matrix calls for a potential (Ve) varying in time slowly in relation to the total erasing time discretely with a stepped wave form between a minimum initial value and a maximum final value is applied directly to the source terminal (S) of the transistors forming the non-volatile memory cells (1). In this manner it is possible to erase any number of memory cells and in particular a very small number. <IMAGE>