| 摘要 |
<p>A data processor (10, 110) includes 32 user registers arranged in two banks (B0, B1) of 16 registers each. 4-bit addressing is provided. A 16-bit map register (20, 120) determines the bank from which an addressed register (81, 118) is selected. This determination is made individually for each address. The map register is readable and writable so that the mapping of addresses to banks is under program control. This arrangement provides for accessing a large number of registers using a short address code; registers remaining addressable after a remapping retain their addresses.</p> |
