发明名称 A LOW CAPACITANCE, ISOTROPICALLY ETCHED ANTIFUSE
摘要 <p>The present invention provides for an integrated circuit antifuse structure having a first metal interconnection line (11), a programming layer (13) over the first interconnection line, an etch stop layer (14) over the programming layer, a sacrificial buffer layer (15) over the etch stop layer (14), an insulating layer over the buffer layer (15), and a second metal interconnection line (18) over the insulating layer. An aperture extends through the insulating layer and the buffer layer (15). The buffer layer (15) has etching characteristics which are different from those of the insulating layer and the etch stop layer (14). This permits the aperture through the insulating layer to be formed with substantially vertical sides and through the buffer layer (15) to be formed with substantially sloped sides. The second interconnection line (18) extends into the aperture to form an antifuse structure with a low capacitance and a consistent programming voltage.</p>
申请公布号 WO1995032523(A1) 申请公布日期 1995.11.30
申请号 US1995006657 申请日期 1995.05.24
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