Sampling clock generating circuit.

摘要

A circuit generates a sampling clock which is used for the A-D conversion of a video signal. A master clock produced by a frequency synthesizer (1) is demultiplied in frequency at dividing ratio NS by a programmable frequency demultiplier (2) which is reset by the horizontal sync signal. The resulting sampling clock can have one of various frequencies depending on the combination of the frequency dividing ratio NM of the frequency synthesizer (1) and the frequency dividing ratio NS of the programmable frequency demultiplier (2) so that it is fit for various video signals.