| 摘要 |
An apparatus and method for protecting the state of a state machine from an unstable clock signal. The apparatus of one embodiment includes a state register having an input and a first output which provides an output signal corresponding to the state of the state machine and a set or reset input coupled, through a logic circuit, to the first output. The logic circuit is coupled to receive a signal indicating the unstable state of the clock signal. The logic circuit is coupled to receive a signal indicating the unstable state of the clock signal. The logic circuit feeds back the output from the first output to the set or reset input to maintain the state in the state register while the clock signal is unstable. An embodiment of the method comprises storing a state in a state register, receiving a first signal indicating an unstable state of the clock signal and feeding back the output from the state register to the set or reset input while the first signal indicates the unstable clock exits. In an alternative embodiment, the output from the state register is fed back to its input while the first signal indicates the unstable clock exits. |
