| 摘要 |
PURPOSE:To improve the soft production efficiency of a process where the sequence logical arithmetic and the numerical arithmetic are mixed by describing the sequence logical arithmetic with a transfer instruction of a macroprocessor. CONSTITUTION:A processor 1 stores the state value, the arithmetic result, etc., of a plant into a memory 11. A bit segmenting/embedding part 12 segments the operation bit to be processed by a sequence logical arithmetic part 17 out of the data of the memory 11 and at the same time embeds the data bit information into the memory 11 with the instruction of an instruction decoder 15. The arithmetic information given from an MPU 2 is decoded by the decoder 15 and stored in an instruction queue 14. Then the sequence arithmetic information stored in the queue 14 is counted by an instruction counter 18. When the count value of the counter 18 reaches the limit level of the queue 14, the counter sends an information transmission inhibiting signal to the MPU 2. |
