| 摘要 |
A signal processing circuit delays a binary periodic input signal. Three series-connected delay devices produce output signals that are delayed in relation to the input signal. The delay of the delay devices can be controlled to a very high degree of accuracy, in that the delay devices include a plurality of mutually identical series-connected delay elements which are manufactured at one and the same time by common process steps in one and the same semiconductor process. A controller compares in a phase detector the phase of the input signal with the phase of the output signal from the last delay device, and on the basis thereof delivers control signals to the delay devices. These control signals control the delay devices in a manner such that an equal number of delay elements will be activated in each of the delay devices, such that the delay devices will have mutually the same delay. The total delay between the input signal and the last output signal exceeds one-half but is less than one and a half periods of the input signal in a first regulating sequence, and the total delay reaches to one period of the input signal in a second regulating sequence.
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