发明名称 METHOD FOR ANALYZING DEFECTIVE BIT OF SEMICONDUCTOR MEMORY
摘要 PURPOSE:To efficiently estimate the type of factors of bit failure and the generation probability by calculating the failure occurrence frequency ratio of both 1-bit and two-bit failures from factors for causing both failures simultaneously and obtaining the relative relationship of the occurrence probability of 1-bit and two-bit failures. CONSTITUTION:A first factor for causing 1-bit failure and a second factor for causing 2-bit failure are extracted (S 1/S2) and a third factor for simultaneously causing the 1-bit and 2-bit failures is extracted (S3). Further, a ratio (k) of the occurrence frequency of 1-bit failure and that of 2-bit failure is calculated (S4). Then, the occurrence probability of 1-bit failure and 2-bit failure obtained from the measurement result of a random access memory is plotted on X-Y coordinates. When the plot point changes in the direction which is parallel to X axis, it is determined that a main cause is only the first factor. When the plot point changes in the direction which is vertical to X axis, it is determined that the main cause is the second factor. Then, when the plot point changes in the direction formed by an angle tan<-1>k, it is determined that the main cause is the third factor.
申请公布号 JPH07312393(A) 申请公布日期 1995.11.28
申请号 JP19940103767 申请日期 1994.05.18
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 HENMI MANABU;AKITANI HIDEO;NAKAYAMA SATOSHI;YOSHINO HIDEO
分类号 H01L21/66;G11C29/00;G11C29/44;H01L21/8244;H01L27/11 主分类号 H01L21/66
代理机构 代理人
主权项
地址