| 摘要 |
A system and method for scoreboarding individual cache line units in order to reduce the cache store-miss penalty is disclosed. Store operations to cache addresses which generate a store-miss are allowed to occur during the same time period that a missing line is being retrieved from memory. The cache memory is divided into a plurality of cache lines, each of the cache lines having a plurality of data units. A store-scoreboard, associated with a selected one of the cache lines, maintains a record of the contents of the plurality of data units within the selected cache line. Memory access performance is improved by allowing stores which miss the cache to complete in advance of the miss copy-in and by allowing multiple stores to the same cache line (being retrieved from memory) to occur without a penalty during the latency period of the store miss. Furthermore, a "safety net" is provided for hinted store instructions. The store-scoreboard provides the infrastructure necessary to allow the computer system to verify whether the instruction stream which contains the hinted store has completed its intended obligation.
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