发明名称 BUS ACCESS CONTROLLER
摘要 <p>PURPOSE:To facilitate an analysis of trouble regarding input and output by monitoring the input and output of a central processor without changing operation environment at all. CONSTITUTION:When a CPU 1 sends out an access request, a control function 36 and a monitoring function 37 start operating at the same time. The control function 36 accesses a main memory 30 or peripheral input/output device 31 at the access request. Then the access result is sent out to the CPU 1 through a CPU bus 3. While the control function 36 is in a series of operations, the monitoring function 37 monitors whether or not the series of processes performed by the control function 36 ends normally and writes the access request and the state of the access by the control function 36 as monitor information 35 in the main memory 30.</p>
申请公布号 JPH07311619(A) 申请公布日期 1995.11.28
申请号 JP19940102935 申请日期 1994.05.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAGUCHI YUKIO
分类号 G06F11/34;G05B23/02;(IPC1-7):G05B23/02 主分类号 G06F11/34
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