| 摘要 |
<p>PURPOSE:To form the clock phase control circuit easy to phase adjustment between a clock signal and a data signal at the time of the logic processing of a high-speed signal. CONSTITUTION:This circuit is provided with N delay means 105 and 107, the 1st selection means 108, pattern generation means 103, the 2nd selection means 101, storage means 102, decision means 104, delay amount decision means 109, delay amount selection signal generation means 111, and the 3rd selection means 110. The 1st selection means 108 can select one of the N delay means 105 or 107 by a delay amount selection signal 23 to be outputted from the 3rd selection means 110. The 2nd selection means 101 can select one of the data signal 10 or 13 by a phase decision control signal 12. The 3rd selection means 110 can select one of the delay amount selection signal 17 or 18 by a phase decision control signal 12.</p> |
