| 摘要 |
A reliable, low cost system for generating precisely aligned pixel clock and index signals for a digital scanning or printing system is based on the use of a phase locked loop multiplier to generate a sampling clock precisely synchronized to the drum position encoder sensor output. The sample clock frequency is chosen to be a large, known multiple M of the pixel clock frequency. The pixel clock is chosen to be the sample clock divided by M, making it the proper frequency. Pixel clock phase is established by resetting, on the trailing edge of an index signal generated by a line start index sensor, a DIVIDED M counter used in deriving the pixel clock from the sample clock. The rising edge of the pixel clock is then established to within +/-(1/M) pixel clock periods of the trailing edge of the index signal.
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