Verfahren zur Herstellung einer Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen

摘要

An arrangement with dynamic MOS transistor gain memory cells has a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are interconnected in series through a common node (20) and the diode structure (11) is connected between the common node and the gate electrode (10) of the memory transistor. In order to produce such an arrangement, the selection transistor and the memory transistor are realized as vertical MOS transistors. A vertical series of correspondingly doped zones (2, 3, 4) in which trenches (5, 6) are generated and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is further produced in particular by LPCVD epitaxy or by molecular-beam epitaxy. Insulating structures are formed by trenches (14, 17, 19).