Clock signal dividing circuit.

摘要

The circuit has a switched division ratio of 4/5 and uses ECL technology, with 3 series flip-flops (2,4,5). The positive output (Q2,Q4) of one flip-flop is coupled to the data input (D4,D5) of the next flip-flop, the clock signals of all flip-flops receiving the clock signal (8,9). An AND gate (3) is inserted between the first 2 flip-flops, its output coupled to the data input (D4) of the second flip-flop (4) and its inputs (A3,B3) coupled to the inverting data outputs of the first and third flip-flop (2,5). A second AND gate (1) precedes the first flip-flop, supplied with a control signal for switching the division ratio and the inverting output of the third flip-flop.