发明名称 |
Buried bit line DRAM cell |
摘要 |
Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.
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申请公布号 |
US5468980(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19940334046 |
申请日期 |
1994.11.04 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
YANG, MING-TZONG;HSUE, CHEN-CHIU;HONG, GARY |
分类号 |
H01L21/8242;H01L27/108;(IPC1-7):H01L27/108;H01L29/76 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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