发明名称 |
Method and apparatus for eliminating branches using conditional move instructions |
摘要 |
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.
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申请公布号 |
US5469551(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19940251626 |
申请日期 |
1994.05.31 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
SITES, RICHARD L.;WITEK, RICHARD T. |
分类号 |
G06F9/30;G06F9/318;G06F9/32;G06F9/38;G06F12/08;(IPC1-7):G06F9/315;G06F15/76 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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