发明名称 Decoding system having parallel-processing capability therein
摘要 An image data decoding system for processing compressed data including variable-length codes and fixed-length codes in digital code series, capable of significantly reducing overall data processing time duration and also reducing a size and scale for a circuit therefor. The image data processing system includes: extracting portion which extracts the variable-length code and the fixed-length code from the digital code series; a processor which processes data based on a value obtained from the digital code series; a self-running decoder which starts to decode the variable-length codes in parallel with data processing in the processor, upon receipt of a start signal from the processor; compare unit which compares the variable-length code and the condition for stopping self-running decoding decoder; and image reconstructing unit which reconstructs image in accordance with a plurality of parameters obtained from the processor and the self-running decoder.
申请公布号 US5469273(A) 申请公布日期 1995.11.21
申请号 US19940184920 申请日期 1994.01.24
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 DEMURA, TATSUHIKO
分类号 H03M7/40;H04N7/26;H04N7/30;H04N7/50;(IPC1-7):H04N1/41 主分类号 H03M7/40
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