发明名称 |
Capacitive coupled summing circuit with signed output |
摘要 |
A summing circuit for executing summing of analog data with sign. The summing circuit includes two serially connected inverters INV1 and INV2, each having a feed back line, and selectively inputs data D1 to D8 to one of the first or the second stages, corresponding to positive/negative sign signals S1 to S8.
|
申请公布号 |
US5469102(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19940196837 |
申请日期 |
1994.02.15 |
申请人 |
YOZAN INC. |
发明人 |
SHOU, GUOLIANG;YANG, WEIKANG;TAKATORI, SUNAO;YAMAMOTO, MAKOTO |
分类号 |
G06G7/14;(IPC1-7):G06G7/42 |
主分类号 |
G06G7/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|