发明名称 |
AC timing asymmetry reduction circuit including summing DC offset voltage with timing signal |
摘要 |
A DC offset voltage is added to the analog timing signal in a peak detection data recovery circuit to cancel the timing asymmetry from a magnetoresistive head signal. An AC timing asymmetry cancellation circuit uses a charge pump, buffer amplifier and resistor divider to produce the proper DC offset voltage automatically.
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申请公布号 |
US5469305(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19930169423 |
申请日期 |
1993.12.17 |
申请人 |
SEAGATE TECHNOLOGY, INC. |
发明人 |
MADSEN, TIMOTHY A.;MACHELSKI, RUSSELL J. |
分类号 |
G11B5/035;G11B5/09;H03F3/45;(IPC1-7):G11B5/09;G11B5/03 |
主分类号 |
G11B5/035 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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