发明名称 |
Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits |
摘要 |
A machine methodology for designing asynchronous circuits utilizes a modular approach for the synthesis of asynchronous circuits from signal transition graphs, partitions the signal transition graph into a number of simpler and more manageable modules. Each modular graph is then individually solved. The results of the small graphs are then integrated together to provide a solution to the asynchronous circuit design problem as defined by a given asynchronous behavioral specification. A satisfiability solver for Boolean output function utilizing a binary decision diagram is incorporated in one embodiment which is comprised of a structural SAT formula preprocessor and a complete, incremental SAT processor which is specifically designed to find an optimal solution. The preprocessor compresses a large size SAT formula representing a circuit into a number of smaller SAT formulas. Each small size SAT formula is then solved by the BDD SAT processor. The results of these subsolutions are then integrated together to contribute to the solution of the original larger design problem.
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申请公布号 |
US5469367(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19940254186 |
申请日期 |
1994.06.06 |
申请人 |
UNIVERSITY TECHNOLOGIES INTERNATIONAL INC. |
发明人 |
PURI, RUCHIR;GU, JUN |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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