| 摘要 |
PURPOSE:To reduce circuit scale and to reduce the number of wiring, regarding a frame synchronization circuit detecting a synchronization pattern based on the data for which a parallel extension to a number of bits (n) which is fewer than the number of bits (m) of the synchronization pattern is performed. CONSTITUTION:This circuit is provided with a shift register 1 outputting parallel extension data as a low order address, a memory 2 reading synchronization pattern state information, load value control information, surface number information and information showing a synchronization pattern detection/non- detection by this low order address and the high order address from an address/ control circuit 4, a detection state comparison circuit 5 comparing the held synchronization pattern state information of the last time and the synchronization pattern state information of this time and updating the held contents according to the comparison result, a surface number information holding part 10 holding surface number information and forming the high order address and a location pulse generation part 8 controlling a selector 13 in accordance with load value control information, selecting the load value of a frame counter 11 and outputting a synchronization pattern location pulse based on the ripple carry of a frame counter 11. |
