发明名称 |
Translator circuit with symmetrical switching delays |
摘要 |
A translator circuit for providing symmetrical switching delays for use with a power line for a differential amplifier having a first signal line and a complementary second signal line, the translator circuit including: a first voltage clamp coupled to the first signal line and to the power line for limiting a voltage differential between the power line and the first signal line; and a second voltage clamp coupled to the power line and the second signal line for limiting a voltage differential between the power line and the second signal line. The translator circuit provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. The translator circuit also provides symmetrical tracking between the rise to rise and the fall to fall delays of an emitter coupled logic to complementary metal-oxide semiconductor translator circuit.
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申请公布号 |
US5469097(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19950438456 |
申请日期 |
1995.05.10 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
HO, KENNETH |
分类号 |
G11C11/409;H01L29/94;H03K5/13;H03K19/003;H03K19/0185;(IPC1-7):H03K5/08;H03K5/12;H03K19/017 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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