发明名称 |
Self-aligned buried channel/junction stacked gate flash memory cell |
摘要 |
An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. The cell structure (110) includes an n- buried channel/junction region (116) which is implanted in a substrate (112) before formation of a tunnel oxide (126) and a stacked gate structure (134). After the formation of the stacked gate structure, a p-type source region (122) is implanted with a large tilt angle in the substrate. Thereafter, n+ drain and n+ source regions (118, 124) are implanted in the substrate so as to be self-aligned to the stacked gate structure. The cell structure of the present invention facilitates scalability to small size and is useful in high density and low voltage power supply applications.
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申请公布号 |
US5468981(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19940299868 |
申请日期 |
1994.09.01 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
HSU, JAMES |
分类号 |
H01L21/8247;H01L29/788;H01L29/792;(IPC1-7):H01L29/78 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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