| 摘要 |
<p>PURPOSE:To provide a timing adjusting circuit which generates an edge of a free timing. CONSTITUTION:A select signal generating circuit (decoder 91) generates select signals s0,... sn before input of an input signal p0, and a select gate circuit is provided with n selecting gates (AND sates 940 to 947 and an OR sate 95) to which pairs of signals p0 and s0, p1 and s1,... pn and sn are inputted. One of signals p0,...pn is outputted from one of these selecting gates, and a select signal holding circuit (flip flop 92) holds select signals s0,... sn until active edges of signals p0,...pn pass respective selecting gates. When the active edge is given to each selecting sate, a delay signal holding circuit (latches 960 to 967) holds the output state of the selecting gate regardless of the change of the select signal until the input to the selecting gate is set to the inactive state.</p> |
