发明名称 |
Memory address and display control apparatus for high definition television |
摘要 |
A memory address and display control apparatus for an high definition television comprising a memory address controller for controlling memory read/write addresses in response to a motion vector and a control signal, the memory address controller having a display read control circuit, a motion compensation read control circuit, and a raster format write control circuit, a memory unit having a previous frame memory for storing a video signal of a previous frame and a present frame memory for storing a video signal of a present frame, a multiplexing circuit for 2 to 1-multiplexing the output addresses from the memory address controller to alternately address the previous frame memory and the present frame memory in the memory unit, an input/output controller for controlling data input/output of the memory unit in response to frame and invert frame signals, a display controller for receiving video data from the memory unit under the control of the input/output controller and displaying the received video data, and a motion compensation circuit for receiving previous frame video data from the memory unit under the control of the input/output controller and adding a DCT coefficient to the received previous frame video data to transform the received previous frame video data into present frame video data.
|
申请公布号 |
US5469228(A) |
申请公布日期 |
1995.11.21 |
申请号 |
US19930174241 |
申请日期 |
1993.12.28 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
KIM, BEOM S.;LEE, JIN H.;KOO, KYOUNG B. |
分类号 |
G06F12/00;G06T1/60;H04N5/14;H04N5/907;H04N7/015;H04N7/26;H04N9/64;H04N11/04;(IPC1-7):H04N7/12;H04N11/02 |
主分类号 |
G06F12/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|