发明名称 PROCEDE ET APPAREIL DE COMMANDE DE MEMOIRE FLASH.
摘要 A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash memory, for making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. The flash memory control method includes the steps of: (a) dividing a memory region of a flash memory into a plurality of sector; and (b) making access to an arbitrary sector of the flash memory by specifying the logical address of the arbitrary sector. Each of the sectors includes a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data.
申请公布号 FR2687811(B1) 申请公布日期 1995.11.17
申请号 FR19930001908 申请日期 1993.02.19
申请人 FUJITSU LTD 发明人 ITOH HIROYUKI;MATSUI NORIYU
分类号 G06F3/08;G06F3/06;G06F11/10;G06F12/00;G06F12/02;G11C16/02;G11C16/10;G11C17/00;(IPC1-7):G06F12/02;G11C16/00 主分类号 G06F3/08
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