| 摘要 |
<p>A Data Cache (22) for a stack based computer (10) comprises an address calculation stage (25), a cache maintenance stage (26) and an arithmetic logic unit stage (27). The computer (10) comprises external memory (21) and a pipelined processor (20). An instruction from an instruction fetch stage (24) is passed to the address calculation stage (25). The address calculation stage (25) translates addresses relative to the top of stack into an absolute address. The cache maintenance stage receives the absolute addresses and determines if data corresponding to the addresses is available in a temporary register in the ALU stage (25). If necessary, the cache maintenance stage (26) injects read from or write to memory instructions into the pipeline (28).</p> |
