发明名称
摘要 PURPOSE:To add the new information to a message at a transfer route by forming this route with a multi-stage switch module having at least one stage and rewriting a part of an input message into the new information by means of each switch module to transmit this information to an output message. CONSTITUTION:A transfer route 2 set among processors 1-1-1-4 is formed with multi-stage switch modules 2-1-2-6. When a message is sent to a processor #11 from a processor #00, a message 3 is first produced in the processor 1-1. The address field 3-1 of the message 3 contains 2 bits, for example, and a binary number 11 is set in this field 3-1. The data to be transferred and the transfer information are set in a data field. The message 3 is sent to the switch module 2-1 through a line l10 as long no busy signal is received from the module 2-1 via a line l30. Each switch module has a switching action with the address of a single bit. A redundant stage 2-1 or 2-2 uses an optional address as the switch information together with a 2nd stage 2-3 or 2-4 using the higher order bit of an address field in a message and a 3rd stage 2-5 or 2-6 using a lower order bit respectively.
申请公布号 JPH07107680(B2) 申请公布日期 1995.11.15
申请号 JP19860249621 申请日期 1986.10.22
申请人 发明人
分类号 G06F15/173 主分类号 G06F15/173
代理机构 代理人
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