发明名称 |
FM MULTIPLEX BROADCASTING RECEIVER |
摘要 |
<p>PURPOSE:To detect frame synchronism at high speed by regarding lateral blocks as the temporary leading blocks of frames, performing longitudinal error correction to deinterleaved data and establishing the frame synchronism while utilizing that correction. CONSTITUTION:A timing generating circuit 72 generates addresses (1) adding deinterleaved longitudinal addresses and designated lateral addresses with the temporary starting block as an origin, reads bits (m) from a data memory 70 and loads them to an error correcting circuit 74 or a continuity monitoring circuit 76. When lateral error correction is finished and a lateral error correction end signal (t) is outputted, a clear signal (n) is applied from the timing generating circuit 72 to the continuity monitoring circuit 76. Then, the continuity monitoring circuit 76 checks whether the (1) is raised at a signal (o) during one frame period or not, and operates so as to eliminate the establishment of wrong synchronism.</p> |
申请公布号 |
JPH07303094(A) |
申请公布日期 |
1995.11.14 |
申请号 |
JP19940094215 |
申请日期 |
1994.05.06 |
申请人 |
SANYO ELECTRIC CO LTD;NIPPON HOSO KYOKAI <NHK> |
发明人 |
YAMASHITA SHIYUUGO;TOMITA YOSHIKAZU;KURODA TORU;TAKADA MASAYUKI;ISOBE TADASHI;YAMADA TSUKASA |
分类号 |
H04L1/00;H03M13/33;H04B14/00;H04J3/06;H04L7/08;(IPC1-7):H04L1/00 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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