| 摘要 |
A CMOS input circuit that has a first inverter stage for comparing non rail-to-rail digital input voltages to a threshold voltage, and producing inverted CMOS output voltages is disclosed. The inverted output voltages are approximately equal to a low CMOS supply voltage plus an offset voltage and a high CMOS supply voltage. The inverter includes PMOS and NMOS transistors that are connected to receive a common input voltage at their gates and to have a common drain current. The PMOS' source is connected to the high supply voltage, and the NMOS' source is connected through a voltage drop circuit element to the low supply voltage. The inverted output voltage is produced at the connection of the PMOS and NMOS transistors' drains. The NMOS and PMOS transistors have gate width and length parameters WN, LN and WP, LP, respectively. The ratio <IMAGE> is selected so that the threshold voltage is set between the maximum low and minimum high input signals for a desired range of high supply voltages. A second logic gate responds to the offset low and high inverted output voltage signals and produces CMOS compatible voltages.
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