| 摘要 |
For digital transitions from one binary logic level to another by frequency or phase shift of an electric carrier wave the modulation sidebands are reduced by performing each transition by means of several phase steps at small intervals. Equal phase steps at varying intervals are preferred over equal intervals between varying phase steps although both procedures can provide a low-bandwidth transition. This procedure is readily incorporated at low cost in frequency synthesizers. The use of a higher-frequency master oscillator (16) followed by a fixed-ratio frequency divider (17) ahead of a variable-ratio frequency divider (18) makes it easy to shift phase or frequency digitally by small quick steps. Another variable-ratio frequency divider (13) is desirable but not essential in the final PLL between a ultimately controlled oscillator (10) and a loop filter (12) connected to a phase discriminator (11). The discriminator (11) and the two variable-ratio frequency dividers (17, 13) require simultaneous or coordinated initialization (line 20). A binary digital signal produces GMSK modulation by means of a processor in which the divider ratios and their timings and sequence are stored. The steps are small enough for the loop filter to provide adequate bandwidth reduction. Steps each produced by a divisor one unit higher than the divisor which keeps the phase constant for the nominal frequency are produced by one cycle of the reference frequency, which corresponds to a number equal to the overall divisor of cycles of the master oscillator.
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