| 摘要 |
<p>PURPOSE: To provide a computer system and a method to control a peripheral bus clock signal via a slave device to which a power saving device is applied. CONSTITUTION: When the system is reset, a BIOS boot code reads a content of a configuration registration MAXLAT in each substitutive bus master. The content of the register indicates a frequency of required access by a specific master to a peripheral bus 102. When the MAXLAT field of each master is read, the system sets a timer according to the MAXLAT value corresponding to a master requiring most frequent access to the peripheral bus. When the master requiring most frequent access to the peripheral bus specifies a maximum wait time, e.g. 2μs, the system sets the timer to start a cycle for each 1μs (a half of specified maximum wait time). When a power management unit 111 decides stop of the peripheral bus clock, the timer starts the cycle.</p> |
