发明名称 |
Adaptive clock skew and duty cycle compensation for a serial data bus |
摘要 |
The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The de-skewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.
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申请公布号 |
US5467464(A) |
申请公布日期 |
1995.11.14 |
申请号 |
US19930028387 |
申请日期 |
1993.03.09 |
申请人 |
APPLE COMPUTER, INC. |
发明人 |
OPRESCU, FLORIN;VAN BRUNT, ROGER |
分类号 |
G06F1/10;G06F1/12;H04L7/00;H04L7/033;H04L7/04;(IPC1-7):H03K5/13 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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