Superscalar processor having bypass circuit for directly transferring result of instruction execution between pipelines without being written to register file

摘要

In a superscalar parallel processor, the execution time for instructions can be reduced, and the performance of instruction processing can be improved. A superscalar parallel processor having a plurality of pipelines arranged to parallelly execute a maximum of N (N>1) instructions includes a bypass circuit for transferring a data output of each step of at least two pipelines between the pipelines.