| 摘要 |
PURPOSE:To prevent the change of the multiplexing position of a frame synchronizing pattern multiplexed with an output signal even at the time of switching from a current line to a standby line. CONSTITUTION:A write address counter 9-m generates a write address AWm in accordance with a select frame pulse F6m. A reference signal delay circuit 10-m outputs a delay reference signal (delay frame pulse) Rm obtained by delaying a reference signal (reference frame pulse) R0 by a certain time. A read address counter 11-m generates a read address ARm in accordance with the delay frame pulse. A select data signal string D6m is written as a stored data signal string in a FIFO memory 12-m in accordance with the write address AWm and the stored data signal string is read out in accordance with the read address ARm to output a changed data signal string D12. Thus, this signal string D12 where the frame synchronizing pattern multiplexing position always has a fixed phase is outputted. |
