| 摘要 |
<p>PURPOSE:To provide a circuit for frame synchronism between asynchronous clocks which properly synchronizes frames even in the case of deviation of the frame pulse signal due to influence of jitter or the like. CONSTITUTION:A means 11 which detects a frame pulse signal FP sent from a transmission means 1 at certain intervals to output detection data ED1, a means 12 which is reset by a reset signal R1 and holds and outputs stable bit data SD1 at the time of supply of detection data ED1 after reset, a means 13 which outputs data ED1 as a load signal LO1 as it is at the time when data SD1 is not supplied yet, a means 14 which goes to '0' at the time of supply of the signal LO1 and repeatedly counts one period from '0' to '1' and has one period equal to the sending interval of the signal FP, and a means 15 which detects the signal FP at the time of supply of (n-1) and (n) of a counted value CD1 and outputs a signal R1 at the time when it is not detected are provided to constitute a reception means 10 for frame synchronization.</p> |
