| 摘要 |
<p>PURPOSE:To provide the power saving system of the CPU system which maintains the degree of freedom of system design and effectively saves the power of the CPU system. CONSTITUTION:The system is equipped with a clock generation part 6 which generates external clocks OCK with plural frequencies synchronized with an input main clock signal MCK, and the respective external clock signals of this generation part are distributed to respective function circuit parts 2. The clock generation part 6 is equipped with a clock frequency division part which generates an external clock signal OCK of frequency corresponding to frequency division ratio setting data BSD from a CPU 1 and an external clock selection part which outputs the external clock signal OCK corresponding to external clock selection data CSD from the CPU 1. Further, a clock generation part 5 which generates a main clock signal MCK is equipped with an oscillation circuit which starts and ends oscillation operation and a switch means which starts and ends the output of the oscillation signal MCK and is set in respective power-saving modes wherein the oscillation operation is started and ended and the output is ended according to the power-saving mode setting data SMD from the CPU 1.</p> |
