| 摘要 |
A computer memory device has a predetermined number of individually addressable storage cells and an internal addressing mechanism for storing a full address that determines which of the predetermined number of individually addressable storage cells will be accessed during a next memory access operation. The internal addressing mechanism includes a number of address segment registers whose concatenated outputs represent the full address. The width of each of the address segment registers is equal to the size of the address bus that couples the memory device to a processor. Mode control signals, sent by the processor, instruct the memory device to load a particular one of the address segment registers, thereby eliminating the need to include a number of address pins equal to the number of bits in the full address. The mode control signals may also be encoded to instruct the memory device to increment the full address for use during a next memory operation, or to use one or more previously read data bytes to either replace or modify existing values stored in the address segment registers, thereby reducing the number of address bits which must be communicated from the processor to the memory device. Additional pin and energy savings may be achieved by multiplexing the data and address lines. The mode control signals may be encoded to indicate how the multiplexed interface is being used during any particular memory cycle. A compatible processor includes logic for generating the various mode control signals during memory operations. |
