Output circuit for integrated circuit.

摘要

An MOS p-type transistor (11) and MOS n-type transistor (12) are connected in parallel with an MOS n-type (13) validation transistor forming an output stage (1). Validation is between the voltage feed and the reference. Variable input logic is applied to the two transistors, giving an output from the validation transistor. A circuit (2,4) feeds each of the parallel transistors, the first circuit providing intermediate switching (TRISP) and the second circuit switching the second transistor. The feed circuit provide a counter reaction circuit reducing switch times.