发明名称 |
Method for programming floating-gate memory cells. |
摘要 |
The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction. <IMAGE> |
申请公布号 |
EP0646933(A3) |
申请公布日期 |
1995.11.02 |
申请号 |
EP19940105553 |
申请日期 |
1994.04.11 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
KAYA,CETIN;HOLLAND,WAYLAND B.;MEZZENNER,RABAH |
分类号 |
G11C17/00;G11C16/04;G11C16/12 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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