Phasenregelschleifenschaltung.

摘要

A phase-locked loop circuit comprises a controller (30) for driving a low-pass filter (18) continually in response to a signal from a phase comparator (14) which compares a divided frequency (fN) of an oscillation frequency (f0) with a reference frequency (fr). The low-pass filter supplies a control voltage (VT) having a changing rate higher than an ordinary rate to a voltage controlled oscillator (10) so that the divided frequency becomes equal to the reference frequency. Consequently, the lock-up time is sufficiently shortened, when a frequency dividing ratio (N) is changed.