发明名称 Semiconductor memory device including means for checking the operation of an internal address generator
摘要 A data string representing the initial value (00000000) is supplied to an internal address generator. The internal address initial setting load signal is input to cause the internal address generator to be initialized. Then, a first detection signal is read out from the first detection circuit, and the level of the signal is checked. If the level of the first detection signal is HIGH, it indicates that the initialization of the internal address generator has been conducted normally. If the level of the first detection signal is LOW, it indicates that the initialization of the internal address generator has not been conducted normally. Thereafter, the count-up operation of the internal address generator is conducted while a count-up signal is supplied a predetermined number of times (255 times) to the internal address generator. A second detection signal is read out from a second detection circuit, and the level of the signal is checked. If the level of the second detection signal is HIGH, it indicates that the count-up operation of the internal address generator has normally been conducted. If the level of the second detection signal is LOW, it indicates that the count-up operation of the internal address generator has not been conducted normally.
申请公布号 US5463635(A) 申请公布日期 1995.10.31
申请号 US19940234600 申请日期 1994.04.28
申请人 SHARP KABUSHIKI KAISHA 发明人 KUMAZAWA, RYOICHI;NAWAKI, MASARU
分类号 G11C29/00;G01R31/28;G11C11/401;G11C29/02;G11C29/20;G11C29/56;(IPC1-7):G06F11/00;G06F11/30 主分类号 G11C29/00
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