发明名称 Memory device having address translator and comparator for comparing memory cell array outputs
摘要 A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.
申请公布号 US5463751(A) 申请公布日期 1995.10.31
申请号 US19940358688 申请日期 1994.12.19
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 YONEZAWA, HIROKAZU;YAMAGUCHI, SEIJI
分类号 G06F12/10;(IPC1-7):G06F12/10 主分类号 G06F12/10
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