发明名称 Method and apparatus for determining error location
摘要 A circuit for determining locations of the errors that occur during data storage tests each possible error location using an error location polynomial. Accumulating registers of a set of multiplier accumulators are loaded with the components of the error location polynomial at the start of each 120-byte word to be tested. The output signals of the accumulating registers are transferred to an XOR checksum circuit. If the output of the XOR checksum circuit is determined to be zero, the current byte of the tested word is considered to be an error location. An external clock signal corresponding to the consecutive bytes to be tested saves the outputs of the unary multipliers for multiplying by the Galois field elements alpha 123- alpha 131, through a feedback loop to the multiplier accumulating registers.
申请公布号 US5463642(A) 申请公布日期 1995.10.31
申请号 US19930082867 申请日期 1993.06.29
申请人 MITSUBISHI SEMICONDUCTOR AMERICA, INC. 发明人 GIBBS, VICKIE L.;KAO, ROM-SHEN
分类号 G11B20/18;H03M13/15;(IPC1-7):H03M13/00 主分类号 G11B20/18
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