发明名称 CLOCK INTERMITTENT DEMODULATION CIRCUIT AND INTERMITTENT RECEPTION DEMODULATION DEVICE
摘要 PURPOSE:To provide an intermittent demodulation circuit which can quickly start the phase control and can shorten the ON time of a receiver by providing a circuit which stops in a power OFF state after holding the frequency and the phase of a symbol clock and a circuit which always oscillates. CONSTITUTION:A reference clock 36 is always oscillated, and the power supplies of other circuits are intermittently turned on and off to wait for reception of the clocks 36. In a power ON state, a reception circuit 32 and a detection identifying circuit 34 demodulate the received signals and send the timing detection signals contained in the demodulation data to a BTR circuit 35 as the clock control signals. A U/P counter 47 operates by the output of a phase detector 46 to change the dividion ratio of a variable division circuit 48 and to set the phsse difference at zero between a symbol clock fS and the signal 39. When the power supply is turned off, the output of the counter 47 is set at zero and the division ratio is set at 1/n. The clock fS keeps its phase that is set right before the signal 39 is cut. In a power ON state, the phase is detected in a state set right before the power supply is turned off. Thus the phase control is quickly started.
申请公布号 JPH07288499(A) 申请公布日期 1995.10.31
申请号 JP19940075916 申请日期 1994.04.14
申请人 MITSUBISHI ELECTRIC CORP 发明人 OGA TETSUAKI
分类号 H04B7/26 主分类号 H04B7/26
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